A 40Gb/s Linear Redriver with Multi-Band Equalization in 130nm SiGe BiCMOS

TL;DR

This paper presents a 40Gb/s linear redriver circuit in 130nm SiGe BiCMOS that uses multi-band equalization techniques to extend high-speed wireline link reach by compensating for channel losses.

Contribution

It introduces a novel multi-band equalization approach combining programmable peaking, CTLE, and VGA stages in a compact design for high-speed data transmission.

Findings

Achieves 23.5dB peaking at 20GHz

Supports 1Vppd linear output swing

Consumes 115.2mW power per channel

Abstract

A linear redriver circuit implements multi-band equalization techniques to efficiently compensate for high-frequency channel loss and extend high-speed wireline link reach. Input and output stage emitter-follower buffers with dual AC and DC paths provide programmable low-frequency peaking for channel skin effect, while a continuous-time linear equalizer (CTLE) utilizes RC degeneration in the input stage for mid-band peaking and a subsequent feedback structure contributes to additional high-frequency peaking to compensate for the additional dielectric loss effects. A variable-gain amplifier (VGA) stage provides up to 7.1dB tunable gain and utilizes negative capacitive loads for bandwidth extension. Input and output return loss of -11.0dB and -12.2dB is respectively achieved at 20GHz with input and output T-coil stages that distribute the ESD circuitry capacitance. Fabricated in a 130nm SiGe BiCMOS process, the redriver achieves 23.5dB max peaking at 20GHz and supports a 1Vppd linear output swing. Per-channel power consumption is 115.2mW from a 1.8V supply.