Silicon edge-dot architecture for quantum computing with global control and integrated trimming

TL;DR

This paper proposes a scalable silicon-based quantum computing architecture that uses global control and integrated trimming to reduce complexity and address device variation, advancing the development of fault-tolerant quantum processors.

Contribution

It introduces a silicon edge-dot architecture combining planar and 3D silicon technologies with global control and integrated trimming, enhancing scalability and fault tolerance.

Findings

Architecture supports surface code for fault-tolerance

Global control reduces processor complexity

Integrated trimming addresses device variation

Abstract

A scalable quantum information processing architecture based on silicon metal-oxide-semiconductor technology is presented, combining quantum hardware elements from planar and 3D silicon-on-insulator technologies. This architecture is expressed in the ``unit cell'' approach, where tiling cells in two dimensions and allowing inter-cellular nearest-neighbour interactions makes the architecture compatible with the surface code for fault tolerant quantum computation. The architecture utilises global control methods, substantially reducing processor complexity with scale: Single-qubit control is achieved using globally applied spin-resonance techniques and two-qubit interactions are mediated by large quantum dots. Further, a solution to device variation is proposed through integration of electronics for individual trimming of quantum dot voltage references. Such a combined set of solutions addresses several major barriers to scaling quantum machines within completely silicon based architectures.