EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit

TL;DR

This paper introduces an approximation-based circuit design for STT-RAM that significantly reduces write energy and latency while maintaining robustness against errors and process variations.

Contribution

It proposes a novel approximation technique leveraging stochastic switching in STT-RAM to improve energy efficiency and speed, with added robustness analysis.

Findings

33.04% reduction in write energy

5.47% reduction in write latency

3.7% area overhead

Abstract

Spin Transfer Torque Random Access Memory (STT-RAM) has garnered interest due to its various characteristics such as non-volatility, low leakage power, high density. Its magnetic properties have a vital role in STT switching operations through thermal effectiveness. A key challenge for STT-RAM in industrial adaptation is the high write energy and latency. In this paper, we overcome this challenge by exploiting the stochastic switching activity of STT-RAM cells and, in tandem, with circuit-level approximation. We enforce the robustness of our technique by analyzing the vulnerability of write operation against radiation-induced soft errors and applying a low-cost improvement. Due to serious reliability challenges in nanometer-scale technology, the robustness of the proposed circuit is also analyzed in the presence of CMOS and magnetic tunnel junction (MTJ) process variation. Compared to the state-of-the-art, we achieved 33.04% and 5.47% lower STT-RAM write energy and latency, respectively, with a 3.7% area overhead, for memory-centric applications.