ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication

TL;DR

ReSiPI is a reconfigurable silicon-photonic 2.5D chiplet network that dynamically manages traffic and power, significantly reducing latency, power consumption, and energy use in interposer communication.

Contribution

This work introduces ReSiPI, a novel reconfigurable and power-efficient silicon photonic interposer network with dynamic traffic management using PCMs, advancing 2.5D chiplet communication technology.

Findings

37% lower latency compared to prior networks

25% power reduction in the interposer network

53% energy minimization achieved

Abstract

2.5D chiplet systems have been proposed to improve the low manufacturing yield of large-scale chips. However, connecting the chiplets through an electronic interposer imposes a high traffic load on the interposer network. Silicon photonics technology has shown great promise towards handling a high volume of traffic with low latency in intra-chip network-on-chip (NoC) fabrics. Although recent advances in silicon photonic devices have extended photonic NoCs to enable high bandwidth communication in 2.5D chiplet systems, such interposer-based photonic networks still suffer from high power consumption. In this work, we design and analyze a novel Reconfigurable power-efficient and congestion-aware Silicon Photonic 2.5D Interposer network, called ReSiPI. Considering run-time traffic, ReSiPI is able to dynamically deploy inter-chiplet photonic gateways to improve the overall network congestion. ReSiPI also employs switching elements based on phase change materials (PCMs) to dynamically reconfigure and power-gate the photonic interposer network, thereby improving the network power efficiency. Compared to the best prior state-of-the-art 2.5D photonic network, ReSiPI demonstrates, on average, 37% lower latency, 25% power reduction, and 53% energy minimization in the network.