HWGN2: Side-channel Protected Neural Networks through Secure and Private Function Evaluation
Mohammad Hashemi, Steffi Roy, Domenic Forte, Fatemeh Ganji

TL;DR
This paper introduces HWGN2, a hardware-implemented neural network accelerator on FPGA that enhances side-channel resistance using cryptographic secure function evaluation, offering a trade-off between security and resource efficiency.
Contribution
HWGN2 applies garbled circuits for neural network acceleration, achieving significant reductions in logic and memory use while providing side-channel and input privacy protections.
Findings
Achieves up to 62.5x fewer logical units
Uses 66x less memory than state-of-the-art
Demonstrates side-channel resistance via TVLA tests
Abstract
Recent work has highlighted the risks of intellectual property (IP) piracy of deep learning (DL) models from the side-channel leakage of DL hardware accelerators. In response, to provide side-channel leakage resiliency to DL hardware accelerators, several approaches have been proposed, mainly borrowed from the methodologies devised for cryptographic implementations. Therefore, as expected, the same challenges posed by the complex design of such countermeasures should be dealt with. This is despite the fact that fundamental cryptographic approaches, specifically secure and private function evaluation, could potentially improve the robustness against side-channel leakage. To examine this and weigh the costs and benefits, we introduce hardware garbled NN (HWGN2), a DL hardware accelerator implemented on FPGA. HWGN2 also provides NN designers with the flexibility to protect their IP in…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · Cryptographic Implementations and Security · Advanced Memory and Neural Computing
