Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM

TL;DR

This paper introduces two novel approaches for implementing stateful logic in spin-orbit torque MRAM, leveraging device separation and voltage-gated switching, supported by SPICE simulation evaluations.

Contribution

It proposes two new methods for stateful logic in SOT-MRAM, utilizing standard memory structures and voltage-gated switching, with detailed array designs and simulation validation.

Findings

Successful simulation of logic operations with process variation.

Demonstrated potential for denser memory arrays using voltage-gated SOT switching.

Validation of approaches through SPICE simulations.

Abstract

Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spin orbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays. We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.