Digital-analog co-design of the Harrow-Hassidim-Lloyd algorithm

TL;DR

This paper presents a co-designed digital-analog quantum processor for the HHL algorithm, reducing circuit depth and noise, and providing a systematic implementation of the matrix inverse subroutine for near-term quantum devices.

Contribution

It introduces a systematic method for implementing the HHL subroutine, a co-designed quantum processor architecture, and a digital-analog approach to enhance feasibility on current quantum hardware.

Findings

Depth scales as O(ε^{-1}) with precision

Reduces number of SWAP gates in the architecture

Merges co-design with digital-analog to lower noise

Abstract

The Harrow-Hassidim-Lloyd quantum algorithm was proposed to solve linear systems of equations $A\vec{x} = \vec{b}$ and it is the core of various applications. However, there is not an explicit quantum circuit for the subroutine which maps the inverse of the problem matrix $A$ into an ancillary qubit. This makes challenging the implementation in current quantum devices, forcing us to use hybrid approaches. Here, we propose a systematic manner to implement this subroutine, which can be adapted to other functions $f(A)$ of the matrix $A$, we present a co-designed quantum processor which reduces the depth of the algorithm, and we introduce its digital-analog implementation. The depth of our proposal scales with the precision $\epsilon$ as $\mathcal{O}(\epsilon^{-1})$, which is bounded by the number of samples allowed for a certain experiment. The co-design of the Harrow-Hassidim-Lloyd algorithm leads to a "kite-like" architecture, which allows us to reduce the number of required SWAP gates. Finally, merging a co-design quantum processor architecture with a digital-analog implementation contributes to the reduction of noise sources during the experimental realization of the algorithm.