Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications

TL;DR

Dalorex is a hardware-software co-design that enables high parallelism and energy efficiency for memory-bound graph and linear algebra workloads, scaling beyond 16,000 cores with local memory and traffic-aware scheduling.

Contribution

Dalorex introduces a novel distributed-memory architecture, task-based programming model, and traffic-optimized network to significantly improve scalability and efficiency for irregular memory access applications.

Findings

Achieves strong scaling with over 16,000 cores.

Improves performance and energy efficiency by two orders of magnitude over prior PIM work.

Supports scalable graph and sparse linear algebra workloads.

Abstract

Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching, decoupling, or pipelining can mitigate memory latency and improve core utilization, memory bottlenecks persist due to limited off-chip bandwidth. Approaches doing processing in-memory (PIM) with Hybrid Memory Cube (HMC) overcome bandwidth limitations but fail to achieve high core utilization due to poor task scheduling and synchronization overheads. Moreover, the high memory-per-core ratio available with HMC limits strong scaling. We introduce Dalorex, a hardware-software co-design that achieves high parallelism and energy efficiency, demonstrating strong scaling with >16,000 cores when processing graph and sparse linear algebra workloads. Over the prior work in PIM, both using 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing tile holds an equal amount of data, and all memory operations are local; (2) a task-based parallel programming model where tasks are executed by the processing unit that is co-located with the target data; (3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata; (4) novel traffic-aware task scheduling hardware that maintains high core utilization; and (5) a data placement strategy that improves work balance. This work proposes architectural and software innovations to provide the greatest scalability to date for running graph algorithms while still being programmable for other domains.