AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining

TL;DR

AutoCellLibX is an automated framework that enhances standard cell libraries by mining patterns from gate-level netlists, leading to significant area savings in VLSI design.

Contribution

It introduces the first automated standard cell extension framework that integrates pattern mining and optimization for VLSI design.

Findings

Up to 5 custom cells generated per design

Average 4.49% area reduction achieved

Extension process completed within 1.1 hours per design

Abstract

Custom standard cell libraries can improve the final quality of the corresponding VLSI designs but properly customizing standard cell libraries remains challenging due to the complex characteristics of the VLSI designs. This paper presents an automatic standard-cell library extension framework, AutoCellLibX. It can find a set of standard cell cluster pattern candidates from the post-technology mapping gate-level netlist, with the consideration of standard cell characteristics and technology mapping constraints, based on our high-efficiency frequent subgraph mining algorithm. Meanwhile, to maximize the area benefit of standard cell customization for the given gate-level netlist, AutoCellLibX includes our proposed pattern combination algorithm which can iteratively find a set of gate-level patterns from numerous candidates as the extension part of the given initial standard cell library. To the best of our knowledge, AutoCellLibX is the first automated standard cell extension framework that closes the optimization loop between the analysis of gate-level netlist and standard cell library customization for VLSI design productivity. The experiments with FreePDK45 library and benchmarks from various domains show that AutoCellLibX can generate the library extension with up to 5 custom standard cells within 1.1 hours for each of the 31 benchmark designs and the resultant extension of the standard cell library can save design area by 4.49% averagely.