A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids

TL;DR

This paper introduces a flexible, automatic CMOS layout generation framework that dynamically creates templates and grids, improving efficiency and adaptability for various design requirements and process-specific constraints.

Contribution

It extends existing template-and-grid methods with dynamic creation, virtual instances, and advanced post-processing, enabling more effective and adaptable layout generation.

Findings

Automatically generates DRC/LVS clean layouts in multiple CMOS technologies.

Supports dynamic adjustment of templates and grids during runtime.

Enhances generator description with circular grid indexing and conditional operators.

Abstract

This paper presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology with the following additional techniques applied to produce optimal layouts more effectively. First, layout templates and grids are dynamically created and adjusted during runtime to serve various structural, functional, and design requirements. Virtual instances support the dynamic template-and-grid-based layout generation process. The framework also implements various post-processing functions to handle process-specific requirements efficiently. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description capability is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to various design examples and generates DRC/LVS clean layouts automatically in multiple CMOS technologies.