Hardware-Efficient Template-Based Deep CNNs Accelerator Design

TL;DR

This paper presents a scalable, hardware-efficient FPGA-based CNN accelerator design that optimizes performance-resource trade-offs using template-based methods and fixed-point quantization, demonstrated on popular neural networks.

Contribution

It introduces a novel template-based design methodology for FPGA CNN accelerators that optimizes performance and resource utilization for edge devices.

Findings

Achieved 230 GOP/s peak performance at 200 MHz.

Validated the design on AlexNet, VGG16, and LeNet networks.

Outperformed previous FPGA implementations on Ultra96.

Abstract

Acceleration of Convolutional Neural Network (CNN) on edge devices has recently achieved a remarkable performance in image classification and object detection applications. This paper proposes an efficient and scalable CNN-based SoC-FPGA accelerator design that takes pre-trained weights with a 16-bit fixed-point quantization and target hardware specification to generate an optimized template capable of achieving higher performance versus resource utilization trade-off. The template analyzed the computational workload, data dependency, and external memory bandwidth and utilized loop tiling transformation along with dataflow modeling to convert convolutional and fully connected layers into vector multiplication between input and output feature maps, which resulted in a single compute unit on-chip. Furthermore, the accelerator was examined among AlexNet, VGG16, and LeNet networks and ran at 200-MHz with a peak performance of 230 GOP/s depending on ZYNQ boards and state-space exploration of different compute unit configurations during simulation and synthesis. Lastly, our proposed methodology was benchmarked against the previous development on Ultra96 for higher performance measurement.