PA-PUF: A Novel Priority Arbiter PUF
Simranjeet Singh, Srinivasu Bodapati, Sachin Patkar, Rainer Leupers,, Anupam Chattopadhyay, Farhad Merchant

TL;DR
This paper introduces PA-PUF, a novel physically unclonable function based on a 3-input priority arbiter, demonstrating high reliability, good uniqueness, and improved efficiency over existing designs.
Contribution
It presents a new PA-PUF design utilizing a 3-input priority arbiter with configurable challenge-response pairs, achieving superior performance and efficiency.
Findings
100% reliability after error correction
Uniqueness of 49.63%
Superior implementation efficiency
Abstract
This paper proposes a 3-input arbiter-based novel physically unclonable function (PUF) design. Firstly, a 3-input priority arbiter is designed using a simple arbiter, two multiplexers (2:1), and an XOR logic gate. The priority arbiter has an equal probability of 0's and 1's at the output, which results in excellent uniformity (49.45%) while retrieving the PUF response. Secondly, a new PUF design based on priority arbiter PUF (PA-PUF) is presented. The PA-PUF design is evaluated for uniqueness, non-linearity, and uniformity against the standard tests. The proposed PA-PUF design is configurable in challenge-response pairs through an arbitrary number of feed-forward priority arbiters introduced to the design. We demonstrate, through extensive experiments, reliability of 100% after performing the error correction techniques and uniqueness of 49.63%. Finally, the design is compared with the…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · Integrated Circuits and Semiconductor Failure Analysis · VLSI and Analog Circuit Testing
