Towards a Low-SWaP 1024-beam Digital Array: A 32-beam Sub-system at 5.8 GHz
Arjuna Madanayake, Viduneth Ariyarathna, Suresh Madishetty, Sravan, Pulipati, R. J. Cintra, Diego Coelho, Ra\'iza Oliveira, F\'abio M. Bayer,, Leonid Belostotski, Soumyajit Mandal, Theodore S. Rappaport

TL;DR
This paper presents a low-complexity, multiplier-free digital beamforming architecture for millimeter wave communications, enabling efficient generation of 1024 digital beams with reduced power and area, suitable for real-time FPGA implementation.
Contribution
It introduces a novel multiplierless 32-point DFT approximation for multibeam beamforming, significantly reducing circuit complexity and power consumption for large-scale beam systems.
Findings
Achieved 46% reduction in chip area
Reduced dynamic power consumption by 55%
Real-time 1024-beam generation demonstrated on FPGA
Abstract
Millimeter wave communications require multibeam beamforming in order to utilize wireless channels that suffer from obstructions, path loss, and multi-path effects. Digital multibeam beamforming has maximum degrees of freedom compared to analog phased arrays. However, circuit complexity and power consumption are important constraints for digital multibeam systems. A low-complexity digital computing architecture is proposed for a multiplication-free 32-point linear transform that approximates multiple simultaneous RF beams similar to a discrete Fourier transform (DFT). Arithmetic complexity due to multiplication is reduced from the FFT complexity of for DFT realizations, down to zero, thus yielding a 46% and 55% reduction in chip area and dynamic power consumption, respectively, for the case considered. The paper describes the proposed 32-point DFT…
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