Towards Programmable Memory Controller for Tensor Decomposition

TL;DR

This paper proposes a custom FPGA-based memory controller to accelerate the sparse MTTKRP kernel in tensor decomposition, addressing irregular memory access challenges for improved efficiency.

Contribution

It introduces a novel design approach for a programmable memory controller on FPGA tailored for sparse MTTKRP acceleration in tensor decomposition.

Findings

Custom memory controller improves MTTKRP performance.

Design explores parameter space for optimal FPGA implementation.

Enhances energy efficiency and parallelism in tensor computations.

Abstract

Tensor decomposition has become an essential tool in many data science applications. Sparse Matricized Tensor Times Khatri-Rao Product (MTTKRP) is the pivotal kernel in tensor decomposition algorithms that decompose higher-order real-world large tensors into multiple matrices. Accelerating MTTKRP can speed up the tensor decomposition process immensely. Sparse MTTKRP is a challenging kernel to accelerate due to its irregular memory access characteristics. Implementing accelerators on Field Programmable Gate Array (FPGA) for kernels such as MTTKRP is attractive due to the energy efficiency and the inherent parallelism of FPGA. This paper explores the opportunities, key challenges, and an approach for designing a custom memory controller on FPGA for MTTKRP while exploring the parameter space of such a custom memory controller.