Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?
Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi

TL;DR
This paper investigates the impact of small device variations in computing-in-memory neural network accelerators, highlighting potential drastic accuracy drops in safety-critical systems and the inadequacy of existing mitigation methods for worst-case scenarios.
Contribution
It formulates the worst-case performance problem under device variations and proposes a method to identify the specific variation combinations causing maximum performance degradation.
Findings
Small device variations can drastically reduce DNN accuracy.
Existing methods are ineffective in improving worst-case performance.
Worst-case performance considerations are crucial for safety-critical applications.
Abstract
Computing-in-Memory (CiM) architectures based on emerging non-volatile memory (NVM) devices have demonstrated great potential for deep neural network (DNN) acceleration thanks to their high energy efficiency. However, NVM devices suffer from various non-idealities, especially device-to-device variations due to fabrication defects and cycle-to-cycle variations due to the stochastic behavior of devices. As such, the DNN weights actually mapped to NVM devices could deviate significantly from the expected values, leading to large performance degradation. To address this issue, most existing works focus on maximizing average performance under device variations. This objective would work well for general-purpose scenarios. But for safety-critical applications, the worst-case performance must also be considered. Unfortunately, this has been rarely explored in the literature. In this work, we…
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