Implementing packet trimming support in hardware

TL;DR

This paper explores implementing packet trimming in existing programmable switches, particularly Tofino ASICs, to reduce latency and improve datacenter network performance without hardware redesign.

Contribution

It demonstrates that packet trimming can be approximated and integrated into existing switch hardware and software stacks, enabling low-latency, lossless metadata transmission.

Findings

Trimming can be closely approximated in Tofino switches

Packet trimming can be integrated into production switch software

Implementation reduces latency and loss in datacenter networks

Abstract

Packet trimming is a primitive that has been proposed for datacenter networks: to minimize latency, switches run small queues; when the queue overflows, rather than dropping packets the switch trims off the packet payload and either forwards the header to the destination or back to the source. In this way a low latency network that is largely lossless for metadata can be built. Ideally, trimming would be implemented as a primitive in switch ASICs, but hardware development cycles are slow, costly, and require demonstrated customer demand. In this paper we investigate how trimming can be implemented in existing programmable switches which were not designed with trimming in mind, with a particular focus on a P4 implementation on the Tofino switch ASIC. We show that it is indeed possible to closely approximate idealized trimming and demonstrate that trimming can be integrated into a production-grade datacenter switch software stack.