Development of a new high-speed data acquisition system prototype for SOI pixel detector using SiTCP-XG, a 10-gigabit Ethernet network processor

TL;DR

This paper presents a high-speed data acquisition prototype for SOI pixel detectors using a 10-gigabit Ethernet network processor, demonstrating stable operation at high transfer rates suitable for advanced imaging applications.

Contribution

Development and testing of a new FPGA-based readout board with SiTCP-XG supporting 10-Gbps Ethernet for improved SOI pixel detector data transfer.

Findings

Stable operation at 682 Mbps transfer rate (100 fps)

Maximum tested transfer rate of 2.4 Gbps (350 fps)

System performance exceeds detector requirements

Abstract

We are developing a new readout board with a newer generation field-programmable gate array (FPGA) and the 10-gigabit ethernet to improve the performance and usability of the current readout board based on the 1-gigabit Ethernet. In this new readout board, the SiTCP-XG network processor supporting 10-gigabit Ethernet was implemented. SiTCP is a network processor circuit running on FPGA, and SiTCP-XG is the newly developed version of the SiTCP that supports 10-gigabit Ethernet. Before developing the new board, we constructed a prototype system using the Xilinx FPGA evaluation board KC705 to evaluate the SiTCP-XG. This prototype system was tested with the SOI pixel detector, which has 425,984 (column 832 x row 512 matrix) pixels and a pixel size of 17 x 17 um at the synchrotron beamlines of the PhotonFactory (KEK). This was the first test of the X-ray imaging for this system. The results showed that this system worked stably with a transfer rate of 682 Mbps (equivalent to a frame rate of 100 fps, limited by detector operation parameters), and also worked stably with a transfer rate of 2.4 Gbps (equivalent to 350 fps, the maximum rate limited by the detector performance). These results suggest that the SiTCP-XG system has sufficient transfer performance to cover the SOIPIX detector performance.