High-throughput decoder of quasi-cyclic LDPC codes with limited precision for continuous-variable quantum key distribution systems

TL;DR

This paper presents a high-throughput FPGA-based quasi-cyclic LDPC decoder with residual error correction, enabling Mbps real-time secret key rate generation in continuous-variable quantum key distribution systems, advancing practical secure communication.

Contribution

It introduces a novel FPGA implementation of a quasi-cyclic LDPC decoder with residual error correction for CV-QKD, achieving unprecedented real-time throughput.

Findings

Achieved 360.92 Mbps and 194.65 Mbps decoding throughput.

Supported real-time secret key rates of 17.97 Mbps and 2.48 Mbps.

Demonstrated feasibility for high-rate real-time CV-QKD deployment.

Abstract

More than Mbps secret key rate was demonstrated for continuous-variable quantum key distribution (CV-QKD) systems, but real-time postprocessing is not allowed, which is restricted by the throughput of the error correction decoding in postprocessing. In this paper, a high-throughput FPGA-based quasi-cyclic LDPC decoder is proposed and implemented to support Mbps real-time secret key rate generation for CV-QKD for the first time. A residual bit error correction algorithm is used to solve the problem of high frame errors rate (FER) caused by the limited precision of the decoder. Specifically, real-time high-speed decoding for CV-QKD systems with typical code rates 0.2 and 0.1 is implemented on a commercial FPGA, and two throughputs of 360.92Mbps and 194.65Mbps are achieved, respectively, which can support 17.97 Mbps and 2.48 Mbps real-time generation of secret key rates under typical transmission distances of 25km and 50km, correspondingly. The proposed method paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.