Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders

TL;DR

This paper introduces two novel CNTFET-based quaternary full adders that utilize voltage levels 0 and Vdd to significantly reduce carry propagation delay in carry propagate adders, outperforming binary implementations.

Contribution

The paper proposes two new CNTFET quaternary full adder designs using voltage levels 0 and Vdd, improving carry propagation efficiency over traditional binary adders.

Findings

Reduced carry propagation delay with voltage level approach

Comparison shows quaternary adders outperform binary in carry propagation

Voltage level method simplifies carry logic implementation

Abstract

In Carry Propagate Adders, carry propagation is the critical delay. For the 1-digit adders that they use, the most efficient scheme is to generate two intermediate carries: C$_{out0}$ ($C_{in}$=0) and $C_{out1}$($C_{in}$=1). Then multiplex them to produce the correct output according to $C_{in}$. For any radix, the carry output has always a logical value 0 or 1. We show that using 0 and $V_{dd}$ levels for input and output carries instead of 0 and $V_{dd}$/3 in quaternary full adders significantly reduce the carry propagation. We compare such a quaternary full adder with binary full adders to implement N-digit carry propagate adders.