Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption

TL;DR

Sealer is a novel in-SRAM encryption engine that leverages SRAM's inherent parallelism to provide high-performance, low-overhead data encryption and decryption, significantly improving throughput and energy efficiency.

Contribution

It introduces Sealer, a low-overhead in-SRAM AES encryption method utilizing SRAM's bitline computational capabilities with minimal circuit modifications.

Findings

Up to 100x throughput-per-area improvement

Consumes 3x less energy than prior solutions

Provides secure data encryption with minimal performance impact

Abstract

To provide data and code confidentiality and reduce the risk of information leak from memory or memory bus, computing systems are enhanced with encryption and decryption engine. Despite massive efforts in designing hardware enhancements for data and code protection, existing solutions incur significant performance overhead as the encryption/decryption is on the critical path. In this paper, we present Sealer, a high-performance and low-overhead in-SRAM memory encryption engine by exploiting the massive parallelism and bitline computational capability of SRAM subarrays. Sealer encrypts data before sending it off-chip and decrypts it upon receiving the memory blocks, thus, providing data confidentiality. Our proposed solution requires only minimal modifications to the existing SRAM peripheral circuitry. Sealer can achieve up to two orders of magnitude throughput-per-area improvement while consuming 3x less energy compared to the prior solutions.