Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm

TL;DR

This paper introduces a hardware-accelerated IIR filter matrix algorithm for noise filtering in neuromorphic vision event streams, achieving over 99% noise removal and high throughput on FPGA hardware.

Contribution

It presents a novel IIR filter matrix algorithm and a low-resource FPGA hardware architecture for efficient noise filtering in neuromorphic vision systems.

Findings

Over 99% noise removal efficiency

Throughput of up to 385.8 million events per second

Validated on Xilinx Zynq UltraScale+ MPSoC hardware

Abstract

Neuromorphic vision is a rapidly growing field with numerous applications in the perception systems of autonomous vehicles. Unfortunately, due to the sensors working principle, there is a significant amount of noise in the event stream. In this paper we present a novel algorithm based on an IIR filter matrix for filtering this type of noise and a hardware architecture that allows its acceleration using an SoC FPGA. Our method has a very good filtering efficiency for uncorrelated noise - over 99% of noisy events are removed. It has been tested for several event data sets with added random noise. We designed the hardware architecture in such a way as to reduce the utilisation of the FPGA's internal BRAM resources. This enabled a very low latency and a throughput of up to 385.8 MEPS million events per second.The proposed hardware architecture was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the Mercury+ XU9 module with the Mercury+ ST1 base board.