A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning

TL;DR

This paper introduces a deep-learning-based pipeline to improve post-silicon tuning by efficiently identifying critical variables, reducing manual effort, and handling complex chip data.

Contribution

It presents a novel neural network approach for variable selection and tuning in post-silicon validation, enhancing efficiency over manual methods.

Findings

Neural networks effectively identify critical tuning variables.

The pipeline reduces manual inspection effort.

Improves tuning efficiency for complex chips.

Abstract

In post-silicon validation, tuning is to find the values for the tuning knobs, potentially as a function of process parameters and/or known operating conditions. In this sense, an more efficient tuning requires identifying the most critical tuning knobs and process parameters in terms of a given figure-of-merit for a Device Under Test (DUT). This is often manually conducted by experienced experts. However, with increasingly complex chips, manual inspection on a large amount of raw variables has become more challenging. In this work, we leverage neural networks to efficiently select the most relevant variables and present a corresponding deep-learning-aided pipeline for efficient tuning.