Multilevel Bidirectional Cache Filter

TL;DR

This paper introduces BiDiFilter, a multilevel cache scheme that reduces SSD write amplification and improves latency by intelligently managing data promotion and demotion using a frequency sketch filter.

Contribution

It presents a novel multilevel caching scheme that controls cache level transitions with a frequency sketch filter and separates recent and frequent items for better performance.

Findings

Achieves a 10x reduction in SSD writes in most cases.

Often improves latency by up to 20%.

Outperforms previous multilevel cache policies.

Abstract

Modern caches are often required to handle a massive amount of data, which exceeds the amount of available memory; thus, hybrid caches, specifically DRAM/SSD combination, become more and more prevalent. In such environments, in addition to the classical hit-ratio target, saving writes to the second-level cache is a dominant factor to avoid write amplification and wear out, two notorious phenomena of SSD. This paper presents BiDiFilter, a novel multilevel caching scheme that controls demotions and promotions between cache levels using a frequency sketch filter. Further, it splits the higher cache level into two areas to keep the most recent and the most frequent items close to the user. We conduct an extensive evaluation over real-world traces, comparing to previous multilevel policies. We show that using our mechanism yields an x10 saving of writes in almost all cases and often improving latencies by up to 20%.