Heterogeneous Multi-core Array-based DNN Accelerator
Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha

TL;DR
This paper analyzes how architectural parameters affect energy and performance in array-based DNN accelerators, proposing a heterogeneous multi-core scheme and algorithms to optimize energy efficiency and processing speed.
Contribution
It introduces a simulation tool for architectural analysis and proposes a heterogeneous multi-core scheme with algorithms for efficient neural network execution.
Findings
Up to 36% energy savings with near-optimal core configurations.
Up to 67% reduction in energy-delay product.
Effective layer distribution algorithm for faster processing.
Abstract
In this article, we investigate the impact of architectural parameters of array-based DNN accelerators on accelerator's energy consumption and performance in a wide variety of network topologies. For this purpose, we have developed a tool that simulates the execution of neural networks on array-based accelerators and has the capability of testing different configurations for the estimation of energy consumption and processing latency. Based on our analysis of the behavior of benchmark networks under different architectural parameters, we offer a few recommendations for having an efficient yet high performance accelerator design. Next, we propose a heterogeneous multi-core chip scheme for deep neural network execution. The evaluations of a selective small search space indicate that the execution of neural networks on their near-optimal core configuration can save up to 36% and 67% of…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAdvanced Memory and Neural Computing · Advanced Neural Network Applications · Ferroelectric and Negative Capacitance Devices
