Towards Effective Depthwise Convolutions on ARMv8 Architecture
Ruochen Hao, Qinglin Wang, Shangfei Yin, Tianyang Zhou, Siqi Shen,, Songzhu Mei, Jie Liu

TL;DR
This paper introduces optimized direct implementations of depthwise convolutions on ARMv8, significantly improving performance by reducing memory overhead and enhancing register reuse in CNN computations.
Contribution
The paper presents novel direct algorithms for depthwise convolutions on ARMv8, utilizing implicit padding and register tiling for better efficiency.
Findings
Achieved 4.88x performance improvement over existing direct implementations.
Achieved 16.4x performance improvement over matrix multiplication-based implementations.
Demonstrated effectiveness on two ARMv8 CPUs with open source libraries and Pytorch.
Abstract
Depthwise convolutions are widely used in lightweight convolutional neural networks (CNNs). The performance of depthwise convolutions is mainly bounded by the memory access rather than the arithmetic operations for classic convolutions so that direct algorithms are often more efficient than indirect ones (matrix multiplication-, Winograd-, and FFT-based convolutions) with additional memory accesses. However, the existing direct implementations of depthwise convolutions on ARMv8 architectures feature a bad trade-off between register-level reuse of different tensors, which usually leads to sub-optimal performance. In this paper, we propose new direct implementations of depthwise convolutions by means of implicit padding, register tiling, etc., which contain forward propagation, backward propagation and weight gradient update procedures. Compared to the existing ones, our new…
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Taxonomy
TopicsAdvanced Neural Network Applications · Tensor decomposition and applications · Parallel Computing and Optimization Techniques
