Design Exploration and Security Assessment of PUF-on-PUF Implementations

TL;DR

This paper explores the design, implementation, and security evaluation of PUF-on-PUF architectures, demonstrating that the security resilience depends on the number of stages in APUFs and the size of PUFs, with experimental validation in CMOS.

Contribution

It provides a comprehensive security assessment of various PUF-on-PUF configurations, highlighting the importance of APUF stages and PUF size for security and reliability.

Findings

DNNs can effectively attack APUFs with fewer stages.

Security resilience improves with APUFs having 6 or more stages.

Optimal bit error rate occurs with 8-stage APUFs in the first layer.

Abstract

We design, implement, and assess the security of several variations of the PUF-on-PUF (POP) architecture. We perform extensive experiments with deep neural networks (DNNs), showing results that endorse its resilience to learning attacks when using APUFs with 6, or more, stages in the first layer. Compositions using APUFs with 2, and 4 stages are shown vulnerable to DNN attacks. We reflect on such results, extending previous techniques of influential bits to assess stage bias in APUF instances. Our data shows that compositions not always preserve security properties of PUFs, the size of PUFs used plays a crucial role. We implemented a testchip in 65 nm CMOS to obtain accurate measurements of uniformity, uniqueness, and response stability for our POP implementations. Measurement results show that minimum bit error rate is obtained when using APUFs with 8 stages in the first layer, while fewer APUF stages lead to a large spread of bit error rate across different chips.