INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling

TL;DR

INTERPLAY is a fast, accurate predictive model that estimates performance degradation in processors with multi-cache way-disabling due to permanent faults, aiding design-time fault tolerance strategies.

Contribution

It introduces a combined analytical and simulation framework that accurately predicts multi-cache fault impacts with significantly reduced computational effort.

Findings

Achieves up to 98.40% prediction accuracy

9.2x faster than exhaustive simulation

Effective for multi-cache fault scenarios

Abstract

Modern and future processors need to remain functionally correct in the presence of permanent faults to sustain scaling benefits and limit field returns. This paper presents a combined analytical and microarchitectural simulation-based framework called INTERPLAY, that can rapidly predict, at design-time, the performance degradation expected from a processor employing way-disabling to handle permanent faults in caches while in-the-field. The proposed model can predict a program's performance with an accuracy of up to 98.40% for a processor with a two-level cache hierarchy, when multiple caches suffer from faults and need to disable one or more of their ways. INTERPLAY is 9.2x faster than an exhaustive simulation approach since it only needs the training simulation runs for the single-cache way-disabling configurations to predict the performance for any multi-cache way-disabling configuration.