Superconducting routing platform for large-scale integration of quantum technologies

TL;DR

This paper presents a superconducting multi-layer routing platform fabricated on 200 mm silicon wafers, enabling scalable integration of quantum chips with improved thermal management, device performance, and signal density for large-scale quantum computing.

Contribution

It introduces a novel multi-layer superconducting routing platform for hybrid quantum chip integration, demonstrating fabrication, testing, and preliminary RF characterization.

Findings

High fabrication yield validated at wafer scale.

Superconducting layers exhibit expected properties at cryogenic temperatures.

Preliminary RF tests show promising passive element performance.

Abstract

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies and low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.