Low-Cost Superconducting Fan-Out with Cell I$_\text{C}$ Ranking

TL;DR

This paper introduces a novel JJ cell boundary ranking method to reduce superconducting fan-out overheads, achieving significant savings in JJ count and resource utilization in superconducting electronics.

Contribution

It proposes a new cell boundary ranking approach using JC current discretization to improve fan-out efficiency in superconducting circuits.

Findings

48% JJ count reduction for fan-out of 1024

43% JJ savings in signal splitting

32% JJ savings in clock splitting

Abstract

Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterparts. At the same time, the scalability and resource utilization of superconducting systems are major concerns. Some of these concerns come from device-level challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. Towards this end, we notice that a considerable fraction of hardware resources are not involved in logic operations, but rather are used for fan-out and buffering purposes. In this paper, we ask if there is a way to reduce these overheads, propose the use of JJs at the cell boundaries to increase the number of outputs that a single stage can drive, and establish a set of rules to discretize critical currents in a way that is conducive to this assignment. Finally, we explore the design trade-offs that the presented approach opens up and demonstrate its promise through detailed analog simulations and modeling analyses. Our experiments indicate that the introduced method leads to a 48% savings in the JJ count for a tree with a fan-out of 1024, as well as an average of 43% of the JJ count for signal splitting and 32% for clock splitting in ISCAS'85 benchmarks.