Bayesian Learning of Parameterised Quantum Circuits

TL;DR

This paper introduces a Bayesian approach to optimize parameterized quantum circuits, improving efficiency and noise resilience by using probabilistic methods and dimension reduction strategies, validated on real quantum hardware.

Contribution

It reformulates variational quantum algorithms as Bayesian inference problems, introducing dimension reduction and posterior sampling techniques for better optimization.

Findings

Faster circuit execution and reduced noise with dimension reduction.

Effective posterior sampling avoiding local optima.

Successful experiments on real quantum hardware.

Abstract

Currently available quantum computers suffer from constraints including hardware noise and a limited number of qubits. As such, variational quantum algorithms that utilise a classical optimiser in order to train a parameterised quantum circuit have drawn significant attention for near-term practical applications of quantum technology. In this work, we take a probabilistic point of view and reformulate the classical optimisation as an approximation of a Bayesian posterior. The posterior is induced by combining the cost function to be minimised with a prior distribution over the parameters of the quantum circuit. We describe a dimension reduction strategy based on a maximum a posteriori point estimate with a Laplace prior. Experiments on the Quantinuum H1-2 computer show that the resulting circuits are faster to execute and less noisy than the circuits trained without the dimension reduction strategy. We subsequently describe a posterior sampling strategy based on stochastic gradient Langevin dynamics. Numerical simulations on three different problems show that the strategy is capable of generating samples from the full posterior and avoiding local optima.