An FPGA-based Solution for Convolution Operation Acceleration

TL;DR

This paper presents an FPGA-based architecture designed to accelerate convolution operations in neural networks, aiming for efficient edge-AI deployment with promising performance metrics.

Contribution

It introduces a novel FPGA IP core architecture for convolution acceleration, compatible across FPGA families, optimized for edge-AI applications.

Findings

Single core achieves 0.224 GOPS

Full utilization yields 4.48 GOPS

Demonstrates feasibility for edge-AI hardware acceleration

Abstract

Hardware-based acceleration is an extensive attempt to facilitate many computationally-intensive mathematics operations. This paper proposes an FPGA-based architecture to accelerate the convolution operation - a complex and expensive computing step that appears in many Convolutional Neural Network models. We target the design to the standard convolution operation, intending to launch the product as an edge-AI solution. The project's purpose is to produce an FPGA IP core that can process a convolutional layer at a time. System developers can deploy the IP core with various FPGA families by using Verilog HDL as the primary design language for the architecture. The experimental results show that our single computing core synthesized on a simple edge computing FPGA board can offer 0.224 GOPS. When the board is fully utilized, 4.48 GOPS can be achieved.