Modeling Defect-Level Switching for Highly-Nonlinear and Hysteretic Electronic Devices
Jiahao Dong, R. Jaramillo

TL;DR
This paper presents an analytical, time-efficient model for defect-level switching devices that captures their nonlinear, hysteretic resistive behavior, enabling better design of memory and neuromorphic circuits.
Contribution
The authors develop an accurate, analytical model for DLS devices based on defect metastability theories, facilitating rapid simulation and inverse design of resistive switching behavior.
Findings
Model accurately describes DLS switching physics.
Simulation of pulse duration and amplitude effects.
Inverse design of programming signals for target resistance states.
Abstract
Previously, we demonstrated hysteretic and persistent changes of resistivity in two-terminal electronic devices based on charge trapping and detrapping at immobile metastable defects [H. Yin, A. Kumar, J.M. LeBeau, and R. Jaramillo, Phys. Rev. Applied 15, 014014 (2021)]; we termed these devices as defect-level switching (DLS) devices. DLS devices feature all-electronic resistive switching and thus are volatile because of the voltage-time dilemma. However, the dynamics of volatile resistive switches may be valuable for emerging applications such as selectors in crosspoint memory, and neuromorphic computing concepts. To design memory and computing circuits using these volatile resistive switches, accurate modeling is essential. In this work we develop an accurate and analytical model to describe the switching physics in DLS devices, based on the established theories of point defect…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Machine Learning and ELM · Advanced Semiconductor Detectors and Materials
