Low-power option Greeks: Efficiency-driven market risk analysis using FPGAs

TL;DR

This paper demonstrates how FPGA acceleration significantly improves the efficiency of complex financial risk analysis models, achieving up to 185 times faster performance and providing valuable insights for computational finance workloads.

Contribution

It introduces optimized FPGA implementations of the Heston model and path reduction techniques, showcasing substantial efficiency gains and practical lessons for reconfigurable architecture applications in finance.

Findings

Achieved 8x to 185x performance improvement over CPUs.

Optimized FPGA implementation of Heston model and path reduction.

Provided insights on numerical precision and energy efficiency.

Abstract

Quantitative finance is the use of mathematical models to analyse financial markets and securities. Typically requiring significant amounts of computation, an important question is the role that novel architectures can play in accelerating these models. In this paper we explore the acceleration of the industry standard Securities Technology Analysis Center's (STAC) derivatives risk analysis benchmark STAC-A2\texttrademark{} by porting the Heston stochastic volatility model and Longstaff and Schwartz path reduction onto a Xilinx Alveo U280 FPGA with a focus on efficiency-driven computing. Describing in detail the steps undertaken to optimise the algorithm for the FPGA, we then leverage the flexibility provided by the reconfigurable architecture to explore choices around numerical precision and representation. Insights gained are then exploited in our final performance and energy measurements, where for the efficiency improvement metric we achieve between an 8 times and 185 times improvement on the FPGA compared to two 24-core Intel Xeon Platinum CPUs. The result of this work is not only a show-case for the market risk analysis workload on FPGAs, but furthermore a set of efficiency driven techniques and lessons learnt that can be applied to quantitative finance and computational workloads on reconfigurable architectures more generally.