Comprehensive Survey of Ternary Full Adders: Statistics, Corrections, and Assessments
Sarina Nemati, Mostafa Haghi Kashani, Reza Faghih Mirzaee

TL;DR
This paper reviews and simplifies ternary full adder designs, highlighting that many can be optimized by adopting partial designs with fewer transistors and better power efficiency, validated through realistic simulations.
Contribution
It provides a comprehensive survey of ternary full adders, identifies opportunities for simplification, and demonstrates improved performance of simplified designs through detailed simulations.
Findings
28.6% of designs are partial TFAs
Simplified TFAs have lower delay and power
Fewer transistors in simplified designs
Abstract
The history of ternary adders goes back to more than six decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This paper conducts a review of TFAs so that one can be familiar with the utilized design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0V or VDD. This way, in a single-VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this…
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Taxonomy
TopicsLow-power high-performance VLSI design · Analog and Mixed-Signal Circuit Design · Advancements in Semiconductor Devices and Circuit Design
