Block-Parallel Systolic-Array Architecture for 2-D NTT-based Fragile Watermark Embedding

TL;DR

This paper introduces a block-parallel systolic-array FPGA architecture for 2-D NTT-based fragile watermark embedding, achieving high throughput suitable for real-time image authentication and security applications.

Contribution

It presents a novel FPGA hardware design with two 2-D special Hartley NTT cores for efficient parallel fragile watermark embedding in digital images.

Findings

Achieves 100 million 4x4 HNTT watermark blocks per second at 100 MHz

Operates effectively on FPGA hardware with real-time processing capabilities

Suitable for high-security, real-time digital image authentication applications

Abstract

Number-theoretic transforms (NTTs) have been applied in the fragile watermarking of digital images. A block-parallel systolic-array architecture is proposed for watermarking based on the 2-D special Hartley NTT (HNTT). The proposed core employs two 2-D special HNTT hardware cores, each using digital arithmetic over $\mathrm{GF}(3)$, and processes $4\times4$ blocks of pixels in parallel every clock cycle. Prototypes are operational on a Xilinx Sx35-10ff668 FPGA device. The maximum estimated throughput of the FPGA circuit is 100 million $4\times4$ HNTT fragile watermarked blocks per second, when clocked at 100 MHz. Potential applications exist in high-traffic back-end servers dealing with large amounts of protected digital images requiring authentication, in remote-sensing for high-security surveillance applications, in real-time video processing of information of a sensitive nature or matters of national security, in video/photographic content management of corporate clients, in authenticating multimedia for the entertainment industry, in the authentication of electronic evidence material, and in real-time news streaming.