On the Simulation of Hypervisor Instructions for Accurate Timing Simulation of Virtualized Systems

TL;DR

This paper introduces a new simulation approach that accurately models hypervisor instructions alongside OS instructions, improving timing accuracy in virtualized system simulations, demonstrated on RISC-V architecture.

Contribution

It proposes a novel method to simulate hypervisor instructions for more precise timing in virtualized system simulators, addressing a key inaccuracy in existing models.

Findings

Enhanced timing accuracy in virtualized system simulation

Successful demonstration on RISC-V architecture

Improved fidelity over existing simulators

Abstract

Architectural simulators help in better understanding the behaviour of existing architectures and the design of new architectures. Virtualization has regained importance and this has put a pressing demand for the simulation of virtualized systems. Existing full-system simulators for virtualized systems simulate the application program instructions and the operating system instructions but abstract the hypercalls or traps to the hypervisor. This leads to inaccuracy in the simulation. This paper proposes an approach to simulate hypervisor instructions in addition to operating system instructions for accurate timing simulation of virtualized systems. The proposed approach is demonstrated by simulating RISC-V binary instructions. The simulator is an execution-driven, functional-first, hardware-based simulator coded in Verilog. The paper concludes that the proposed approach leads to accurate timing simulation of virtualized systems.