C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory

TL;DR

The paper introduces C-AND, a novel ferroelectric FET memory architecture that reduces errors, minimizes disturbances, allows longer bitlines, and saves area by using a mixed writing scheme tailored for asymmetric switching voltages.

Contribution

It proposes the C-AND architecture with a mixed writing scheme for FeFET memory, improving error rates, disturbance reduction, and area efficiency over previous designs.

Findings

Reduces read errors compared to previous architectures.

Enables longer bitlines without increasing errors.

Saves up to 2.92X in memory cell area.

Abstract

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.