Efficient and Lightweight In-memory Computing Architecture for Hardware Security

TL;DR

This paper introduces an in-memory computing architecture using memristors for AES encryption, significantly improving throughput and energy efficiency, thereby enhancing cybersecurity for autonomous vehicles.

Contribution

It presents a novel memristor-based in-memory AES architecture with pipeline design and FPGA implementation, achieving higher performance and energy efficiency over existing solutions.

Findings

~30% power reduction compared to conventional AES hardware

~62% increased throughput over state-of-the-art AES NVM engines

Outperforms existing architectures in throughput and energy efficiency

Abstract

The paper proposes in-memory computing (IMC) solution for the design and implementation of the Advanced Encryption Standard (AES) based cryptographic algorithm. This research aims at increasing the cyber security of autonomous driverless cars or robotic autonomous vehicles. The memristor (MR) designs are proposed in order to emulate the AES algorithm phases for efficient in-memory processing. The main features of this work are the following: a memristor 4bit state element is developed and used for implementing different arithmetic operations for AES hardware prototype; A pipeline AES design for massive parallelism and compatibility targeting MR integration; An FPGA implementation of AES-IMC based architecture with MR emulator. The AES-IMC outperforms existing architectures in both higher throughput, and energy efficiency. Compared with the conventional AES hardware, AES-IMC shows ~30% power enhancement with comparable throughput. As for state-of-the-art AES based NVM engines, AES-IMC has comparable power dissipation, and ~62% increased throughput. By enabling the cost-effective real-time deployment of the AES, the IMC architecture will prevent unintended accidents with unmanned devices caused by malicious attacks, including hijacking and unauthorized robot control.