VWSIM: A Circuit Simulator

TL;DR

VWSIM is a logic-based circuit simulator designed for rapid modeling of RSFQ quantum circuits, with potential extensions to other circuit types and a focus on formal verification.

Contribution

It introduces a formal, ACL2-based simulator for RSFQ circuits that can also handle other circuit families and provides logical guarantees about circuit models.

Findings

Supports modeling of primitive circuit devices like Josephson Junctions

Provides formal guarantees through ACL2 logic

Aims to enable property proving of RSFQ circuit models

Abstract

VWSIM is a circuit simulator for rapid, single-flux, quantum (RSFQ) circuits. The simulator is designed to model and simulate primitive-circuit devices such as capacitors, inductors, Josephson Junctions, and can be extended to simulate other circuit families, such as CMOS. Circuit models can be provided in the native VWSIM netlist format or as SPICE-compatible netlists, which are flattened and transformed into symbolic equations that can be manipulated and simulated. Written in the ACL2 logic, VWSIM provides logical guarantees about each of the circuit models it simulates. Note, our matrix solving and evaluation routines use Common Lisp floating-point numbers, and work is ongoing to admit these models into ACL2. We currently use VWSIM to help us design self-timed, RSFQ-based circuits. Our eventual goal is to prove properties of RSFQ circuit models. The ACL2-based definition of the VWSIM simulator offers a path for specifying and verifying RSFQ circuit models.