Multiplierless Design of Very Large Constant Multiplications in Cryptography

TL;DR

This paper introduces TLL, an approximate algorithm for efficiently implementing very large constant multiplications in cryptography using shift-adds, reducing operations and delay with minimal area overhead.

Contribution

The paper presents TDOLL, a novel approximate algorithm that partitions large constants and optimizes shift-adds design considering delay, improving efficiency in cryptographic multiplications.

Findings

Significant reduction in adder-steps with minimal overhead.

36.6% reduction in gate-level area compared to multiplier-based design.

48.3% reduction in delay with delay-aware optimization.

Abstract

This brief addresses the problem of implementing very large constant multiplications by a single variable under the shift-adds architecture using a minimum number of adders/subtractors. Due to the intrinsic complexity of the problem, we introduce an approximate algorithm, called T\~OLL, which partitions the very large constants into smaller ones. To reduce the number of operations, T\~OLL incorporates graph-based and common subexpression elimination methods proposed for the shift-adds design of constant multiplications. It can also consider the delay of a multiplierless design defined in terms of the maximum number of operations in series, i.e., the number of adder-steps, while reducing the number of operations. High-level experimental results show that the adder-steps of a shift-adds design can be reduced significantly with a little overhead in the number of operations. Gate-level experimental results indicate that while the shift-adds design can lead to a 36.6\% reduction in gate-level area with respect to a design using a multiplier, the delay-aware optimization can yield a 48.3\% reduction in minimum achievable delay of the shift-adds design when compared to the area-aware optimization.