Squeezing and quantum approximate optimization
Gopal Chandra Santra, Fred Jendrzejewski, Philipp Hauke, Daniel J., Egger

TL;DR
This paper explores the connection between variational quantum algorithms and quantum metrology, demonstrating how QAOA can generate highly squeezed states for combinatorial optimization and proposing a new hardware benchmarking metric.
Contribution
It establishes a link between quantum optimization and metrology, showing how QAOA can systematically produce squeezed states and introducing a new figure of merit for quantum hardware performance.
Findings
Highly squeezed states can be generated using QAOA.
Squeezing improves optimization precision in MaxCut problems.
Proposes a new benchmark metric for quantum hardware.
Abstract
Variational quantum algorithms offer fascinating prospects for the solution of combinatorial optimization problems using digital quantum computers. However, the achievable performance in such algorithms and the role of quantum correlations therein remain unclear. Here, we shed light on this open issue by establishing a tight connection to the seemingly unrelated field of quantum metrology: Metrological applications employ quantum states of spin-ensembles with a reduced variance to achieve an increased sensitivity, and we cast the generation of such squeezed states in the form of finding optimal solutions to a combinatorial MaxCut problem with an increased precision. By solving this optimization problem with a quantum approximate optimization algorithm (QAOA), we show numerically as well as on an IBM quantum chip how highly squeezed states are generated in a systematic procedure that can…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum Information and Cryptography · Low-power high-performance VLSI design
