Obfuscating the Hierarchy of a Digital IP

TL;DR

This paper introduces a novel method to obfuscate the hierarchy of digital integrated circuit designs by leveraging logic synthesis optimizations, effectively confusing reverse engineering efforts with minimal overhead.

Contribution

The paper presents a new hierarchy obfuscation technique using conventional synthesis optimizations, enhancing security against reverse engineering in IC designs.

Findings

Obfuscation significantly hampers reverse engineering using DANA.

Some obfuscated designs have minimal performance overhead.

Optimizations create diverse, secure design instances.

Abstract

Numerous security threats are emerging from untrusted players in the integrated circuit (IC) ecosystem. Among them, reverse engineering practices with the intent to counterfeit, overproduce, or modify an IC are worrying. In recent years, various techniques have been proposed to mitigate the aforementioned threats but no technique seems to be adequate to hide the hierarchy of a design. Such ability to obfuscate the hierarchy is particularly important for designs that contain repeated modules. In this paper, we propose a novel way to obfuscate such designs by leveraging conventional logic synthesis. We exploit multiple optimizations that are available in the synthesis tool to create design diversity. Our security analysis, performed by using the DANA reverse engineering tool, confirms the significant impact of these optimizations on obfuscation. Among the many considered obfuscated design instances, users can find options that incur very small overheads while still confusing the work of a reverse engineer.