Routing and Placement of Macros using Deep Reinforcement Learning

TL;DR

This paper proposes a deep reinforcement learning approach for macro routing and placement in chip design, aiming to optimize power, performance, and time, thereby reducing delays and improving market availability.

Contribution

It introduces a novel neural architecture trained with reinforcement learning to effectively place chip macros, addressing a complex and time-consuming task in semiconductor design.

Findings

The method successfully learns to place macros with improved efficiency.

The approach reduces placement time compared to traditional methods.

It demonstrates potential for scalable and adaptable chip placement solutions.

Abstract

Chip placement has been one of the most time consuming task in any semi conductor area, Due to this negligence, many projects are pushed and chips availability in real markets get delayed. An engineer placing macros on a chip also needs to place it optimally to reduce the three important factors like power, performance and time. Looking at these prior problems we wanted to introduce a new method using Reinforcement Learning where we train the model to place the nodes of a chip netlist onto a chip canvas. We want to build a neural architecture that will accurately reward the agent across a wide variety of input netlist correctly.