TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

TL;DR

TopSort is a two-phase FPGA-based sorting accelerator optimized for HBM memory, achieving high throughput and outperforming existing CPU and FPGA sorters by leveraging HBM-specific optimizations.

Contribution

It introduces a novel two-phase sorting architecture that fully exploits HBM bandwidth on FPGAs, with specific optimizations to reduce resource use and enhance performance.

Findings

Sorts up to 4 GB data with 15.6 GB/s throughput

Outperforms state-of-the-art CPU and FPGA sorters by 6.7x and 2.2x

Utilizes all 32 HBM channels effectively

Abstract

The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwidth, as the required on-chip resource usage grows at a much faster rate and would bound the sorting performance in turn. Second, designers need an in-depth understanding of HBM characteristics to effectively utilize the HBM bandwidth. To tackle these challenges, we present TopSort, a novel two-phase sorting solution optimized for HBM-based FPGAs. In the first phase, 16 merge trees work in parallel to fully utilize 32 HBM channels. In the second phase, TopSort reuses the logic from phase one to form a wider merge tree to merge the partially sorted results from phase one. TopSort also adopts HBM-specific optimizations to reduce resource overhead and improve bandwidth utilization. TopSort can sort up to 4 GB data using all 32 HBM channels, with an overall sorting performance of 15.6 GB/s. TopSort is 6.7x and 2.2x faster than state-of-the-art CPU and FPGA sorters.