Real-time semantic segmentation on FPGAs for autonomous vehicles with hls4ml

TL;DR

This paper demonstrates a highly efficient FPGA-based implementation of a compressed ENet neural network for real-time semantic segmentation in autonomous vehicles, achieving low latency and resource use.

Contribution

It introduces a fully-on-chip FPGA deployment of a compressed ENet model with optimized implementation, reducing latency and resource consumption for autonomous driving applications.

Findings

Latency of 4.9 ms per image on FPGA

Resource utilization less than 30% on Xilinx ZCU102

Maintains accuracy with reduced power and resources

Abstract

In this paper, we investigate how field programmable gate arrays can serve as hardware accelerators for real-time semantic segmentation tasks relevant for autonomous driving. Considering compressed versions of the ENet convolutional neural network architecture, we demonstrate a fully-on-chip deployment with a latency of 4.9 ms per image, using less than 30% of the available resources on a Xilinx ZCU102 evaluation board. The latency is reduced to 3 ms per image when increasing the batch size to ten, corresponding to the use case where the autonomous vehicle receives inputs from multiple cameras simultaneously. We show, through aggressive filter reduction and heterogeneous quantization-aware training, and an optimized implementation of convolutional layers, that the power consumption and resource utilization can be significantly reduced while maintaining accuracy on the Cityscapes dataset.