ALICE: An Automatic Design Flow for eFPGA Redaction

TL;DR

ALICE is an automated design flow that partitions hardware designs into reconfigurable and fixed parts, enabling hardware IP protection by obscuring sensitive functionalities in integrated circuits.

Contribution

It introduces a novel automated method for partitioning RTL modules and generating redacted designs for secure hardware fabrication.

Findings

Automates the partitioning of RTL modules for reconfigurable fabrics.

Generates redacted designs that protect intellectual property.

Addresses key EDA challenges in hardware IP protection.

Abstract

Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to completely hide the real functionality of selected design portions unless the configuration string (bitstream) is provided. However, selecting such portions and creating the corresponding reconfigurable fabrics are still open problems. We propose ALICE, a design flow that addresses the EDA challenges of this problem. ALICE partitions the RTL modules between one or more reconfigurable fabrics and the rest of the circuit, automating the generation of the corresponding redacted design.