A Low-latency Communication Design for Brain Simulations

TL;DR

This paper proposes a novel low-latency communication strategy for multi-GPU supercomputers to enhance brain simulation performance, demonstrating significant improvements through experiments on a 2000-GPU system.

Contribution

It introduces a partitioning algorithm and a two-level routing method tailored for efficient low-latency inter-GPU communication in brain simulations.

Findings

Significant reduction in communication latency on supercomputers with 2000 GPUs.

Enhanced simulation speed for a 10-billion-neuron brain model.

Guidelines for communication design in high-performance brain simulations.

Abstract

Brain simulation, as one of the latest advances in artificial intelligence, facilitates better understanding about how information is represented and processed in the brain. The extreme complexity of human brain makes brain simulations only feasible upon high-performance computing platforms. Supercomputers with a large number of interconnected graphical processing units (GPUs) are currently employed for supporting brain simulations. Therefore, high-throughput low-latency inter-GPU communications in supercomputers play a crucial role in meeting the performance requirements of brain simulation as a highly time-sensitive application. In this paper, we first provide an overview of the current parallelizing technologies for brain simulations using multi-GPU architectures. Then, we analyze the challenges to communications for brain simulation and summarize guidelines for communication design to address such challenges. Furthermore, we propose a partitioning algorithm and a two-level routing method to achieve efficient low-latency communications in multi-GPU architecture for brain simulation. We report experiment results obtained on a supercomputer with 2,000 GPUs for simulating a brain model with 10 billion neurons to show that our approach can significantly improve communication performance. We also discuss open issues and identify some research directions for low-latency communication design for brain simulations.