A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization
Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh Jye Jou

TL;DR
This paper presents a low-power, energy-efficient keyword spotting accelerator with in-memory computing and on-chip learning, enabling user customization and achieving high accuracy with minimal energy per decision.
Contribution
It introduces an SRAM-based IMC accelerator with bias compensation, fine-tuning, and error scaling techniques for effective low-precision in-edge learning and customization.
Findings
Achieves 96.71% accuracy with user customization.
Runs on-chip with only 14μJ per decision.
Outperforms state-of-the-art in energy efficiency and customization capability.
Abstract
Keyword spotting has gained popularity as a natural way to interact with consumer devices in recent years. However, because of its always-on nature and the variety of speech, it necessitates a low-power design as well as user customization. This paper describes a low-power, energy-efficient keyword spotting accelerator with SRAM based in-memory computing (IMC) and on-chip learning for user customization. However, IMC is constrained by macro size, limited precision, and non-ideal effects. To address the issues mentioned above, this paper proposes bias compensation and fine-tuning using an IMC-aware model design. Furthermore, because learning with low-precision edge devices results in zero error and gradient values due to quantization, this paper proposes error scaling and small gradient accumulation to achieve the same accuracy as ideal model training. The simulation results show that…
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