Optimization of BDD-based Approximation Error Metrics Calculations

TL;DR

This paper introduces four novel BDD-based algorithms for exact error analysis of approximate arithmetic circuits, significantly speeding up evaluation and enabling more efficient design of approximate hardware.

Contribution

The paper presents new algorithms that improve the speed of error evaluation in approximate circuits without computing absolute values, outperforming standard methods.

Findings

Algorithms are on average three times faster than baseline.

In some cases, algorithms are up to 30 times faster.

Over 49,000 runs validated the performance improvements.

Abstract

Software methods introduced for automated design of approximate implementations of arithmetic circuits rely on fast and accurate evaluation of approximate candidate implementations. To accelerate the evaluation of circuit error, we propose four novel algorithms for the exact worst-case and mean absolute error analysis based on Binary Decision Diagrams. As these algorithms do not compute any absolute values in the characteristic function, which basically compares a candidate approximate circuit with a golden circuit, the error evaluation is significantly faster than the standard BDD-based error analysis. On average, the proposed algorithms are three times faster (in some cases, 30 times faster) than the baseline for 8- to 32-bit approximate adders. These results were obtained from more than 49 thousand runs with different configurations of the method. The proposed error evaluation algorithms are available as an open-source software https://github.com/ehw-fit/bdd-evaluation.