PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting

TL;DR

This paper introduces a programmable CIM processor with a large macro and flexible instruction set, achieving high power efficiency and adaptability for keyword spotting neural networks, reducing latency and supporting various CNN models.

Contribution

It proposes a novel programmable CIM architecture with a single large macro and flexible instructions, improving power efficiency, programmability, and supporting diverse CNN models for keyword spotting.

Findings

Achieves 885.86 TOPS/W power efficiency at 10 MHz.

Reduces latency by 35.9% using pooling write-back.

Supports various binary CNN models with high flexibility.

Abstract

Computing-in-memory (CIM) has attracted significant attentions in recent years due to its massive parallelism and low power consumption. However, current CIM designs suffer from large area overhead of small CIM macros and bad programmablity for model execution. This paper proposes a programmable CIM processor with a single large sized CIM macro instead of multiple smaller ones for power efficient computation and a flexible instruction set to support various binary 1-D convolution Neural Network (CNN) models in an easy way. Furthermore, the proposed architecture adopts the pooling write-back method to support fused or independent convolution/pooling operations to reduce 35.9\% of latency, and the flexible ping-pong feature SRAM to fit different feature map sizes during layer-by-layer execution.The design fabricated in TSMC 28nm technology achieves 150.8 GOPS throughput and 885.86 TOPS/W power efficiency at 10 MHz when executing our binary keyword spotting model, which has higher power efficiency and flexibility than previous designs.